This invention relates to the fabrication of extremely small conducting lines such as gates and, more particularly, to a resistless technique for forming such conducting lines on MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) or MESFET (Metal-Semiconductor Field Effect Transistor) devices.
Density and speed of integrated circuits are advancing rapidly as the Large Scale Integration (LSI) circuits have been replaced with Very Large Scale Integration (VLSI) circuits. Currently these circuits or circuit elements have features of the order of micrometers which are manufactured by delineating patterns to permit plating, etching and doping on a micrometer scale. Though some patterns are defined by direct writing of beams onto a surface, most devices are fabricated utilizing masks. The use of masks usually limits features to about 1 to 2 micrometers in size, whereas direct writing permits features having dimensions of submicrometers.
The features are usually defined by forming apertures in masks through which dopants, metal contacts, and electrodes are added; subsequent selective etching is utilized to form the final microcircuit geometry desired. The mask is generally formed in a layer of organic material called a resist. Problems associated with resist masks include poor resolution, swelling, adherence, pin-holes and lack of repeatability. All these factors limit minimum dimensions. Commercial optical lithographic processes must use complicated multiple organic resist layers to produce circuits with submicrometer geometry.
Recent advances in electron beam lithography have involved the use of direct-writing electron beam tools and systems replacing optical lithography. Electron beam lithography provides faster production of circuits since no masks are required. Though some experimental e-beam resists capable of producing submicrometer lines have been announced, the problems associated with resists remain. Though ion beam lithography, as disclosed in U.S. Pat. No. 4,383,026, offers some advantages over e-beam lithography, such as less backscatter and some improvement in resolution, it is still a polymeric resist-based process subject to many of the limitations previously discussed.
It has been shown that ion beams at certain energy and dose thresholds cause ion-induced mixing at the interface between a thin refractory metal layer and a monocrystalline or polycrystal silicon substrate. This produces a material with different etching properties (Tsai, et al., "Refractory Metal Silicide Formation Induced by As.sup.+ Implantation," Appl. Phys. Lett., Vol. 37, p. 295, 1980). Wang, et al. (J. Vac. Sci. Technol., Vol. 19, (4), p. 1158, 1981) disclose a focused ion beam (FIB) for exposure of an ion sensitive resist. Pankove, et al. ("Bombardment-Induced Corrosion Resistance of Aluminum," Appl. Phys. Lett., Vol. 39, p. 119, July 1981) and Gulkeberger (U.S. Pat. No. 3,982,729) show that after bombardment of aluminum films with various ions, the films resist etching. However, there is no known process in which selective ion mixing has been utilized in the fabrication of semiconductor devices. Prior art semiconductor processing uses either positive or negative organic polymeric resists and pattern transfer techniques involving wet/dry etching or lift-off.
Many integrated circuits comprise interconnected MOSFETs or MESFETs. Integrated circuit chips based on FETs usually contain an interconnect metal layer, a doped polysilicon gate layer (MOS), an implant or a diffusion layer, and an insulating oxide layer. Paths are formed in these layers and contacts are cut through the insulating layer to connect certain points between layers. For example, wherever a path on the polysilicon layer crosses over a thin portion of the oxide layer registered between two doped regions in the implant layer, a MOSFET transistor is formed. Circuits of such transistors, connected by patterned paths on these layers, form the basic circuits from which integrated systems are generated.
The rectangular region where the doped polysilicon crosses between the doped regions is called the gate. The polysilicon gate and the thin layer of oxide beneath it are often utilized to effectively mask the region under the gate during the implant of the two doped regions. The gate, separated from the substrate by the layer of thin oxide, effectively forms a capacitor which acts as a switch. When positive charge exceeds threshold, electrons flow to the implanted region or diffusion layer. The dimension of the gate which separates the doped drain and source regions (known as the length, L) affects both the packing density of circuit elements and the speed of the integrated circuit.